US Patent Office


PAT. NO. Title
1 6,509,785 Voltage regulator circuit for attenuating inductance-induced on chip supply variations
2

6,420,913

Dynamic termination logic driver with improved impedance control
3 6,384,675 Differencing non-overlapped dual-output amplifier circuit
4 6,366,139 Method for an output driver with improved impedance control
5 6,339,351 Output driver with improved impedance control
6 6,316,957 Method for a dynamic termination logic driver with improved impedance control
7 6,297,677 Method for a dynamic termination logic driver with improved slew rate control
8 6,294,924 Dynamic termination logic driver with improved slew rate control
9 6,281,729 Output driver with improved slew rate control
10 6,278,306 Method for an output driver with improved slew rate control
11 6,198,325 Differencing non-overlapped dual-output amplifier circuit
12 6,147,515 Differential receiver
13 6,085,033 Method for determining bit element values for driver impedance control
14 6,069,521 Voltage regulation method for attenuating inductance-induced on-chip supply variations
15 6,060,907 Impedance control circuit
16 6,028,417 Voltage regulator circuit for attenuating inductance-induced on-chip supply variations
17 5,973,547 Self-biasing, offset-nulling power supply monitor circuit
18 5,955,894 Method for controlling the impedance of a driver circuit
19 5,942,919 Differential receiver including an enable circuit
20 5,942,918 Method for resolving differential signals
21 5,790,561 Internal testability system for microprocessor-based integrated circuit